Sriram C. Devi

Parallel Architectures for the Real Time Estimation of Higher Order Moments

May 20, 1998
2:00 PM
422 Snell

Abstract

Higher Order Moments are regarded as important tools in modern signal processing. They are needed to overcome the well known limitations of the auto correlation/power spectrum based second order techniques. However, their computation through multi-dimensional estimation algorithms is compute intensive, thus necessitating an application specific implementation for real time performance. Earlier attempts in deriving parallel architectures for higher order moments estimation have two significant limitations : the in-coming data should be transposed before further processing and the size of the computational structure is data block size dependent.

In this thesis, we have developed a new multi-staged approach for computing the Higher Order Moments. The estimation algorithms are formulated as consecutive matrix multiplication stages with appropriate structure. This decomposition ensures that the data samples are processed as they become available and without transposition. The proposed mathematical formulation is systematically transformed into computational structures by developing Locally Recursive Algorithms (LRAs), deriving the corresponding Dependence Graphs (DGs) and then mapping them to Signal Flow Graphs (SFGs) which could be implemented in silicon. The derived array structures are made data block size independent by computing only a fixed number of significant moment lags and by choosing appropriate space and time transformations. The derived designs are translated into appropriate input for the research tool DG2VHDL (under development by PhD student, Andrew Stone in Prof. Elias Manolakos' group) that produces VHDL models used for behavioral simulation and synthesis.

Thesis Committee:
Prof. E.S. Manolakos (Advisor)
Dr. H. Stellakis (GTE Labs)
Prof. M. Vai