Prasad Mandalapu

Verilog models for synthesizable VLSI array architectures derived from algorithmic specifications

July 30, 2004

ABSTRACT

Automatic derivation of parallel VLSI arrays architectures for domain specific algorithms, such as signal and image processing, would enable DSP algorithm developers with little knowledge of hardware design issues to generate automatically hardware realizations on which they could validate their ideas. DG2VHDL from Northeastern University is a suite of tool that addresses this pressing need. DG2VHDL takes a textual description of the Dependence Graph (DG) of an algorithm and produces synthesizable VLSI array models and testbenches in VHDL. It also allows the user to explore the design space for the array implementation that optimize performance metrics such as latency, area, throughput and power.

VHDL and Verilog are the most widely used Hardware Description Languages (HDL) in the Electronics Design industry. In today's System on Chip (SoC) design environments, a design is comprised of several Intellectual Property (IP) cores provided by different vendors. Many design firms that follow a single language design flow would have to invest in another set of tools if IP cores are available in only one HDL. In such an environment addition of Verilog capability to DG2VHDL makes it a more potent suite of tools.

In our effort to add Verilog capability to DG2VHDL, equivalent (to VHDL) Verilog models for various components of a VLSI array were derived. A Verilog code generation module was added to the tool that not only produces the Verilog models for all array components but also produces the required testbenches to validate its functionality. A number of algorithms of varying complexity, including matrix multiplication, convolution, DWT, LU decomposition, Block Motion Matching Estimation, separable image transforms etc. were captured and implemented in both VHDL and Verilog. The synthesized Verilog models were compared to the synthesized VHDL structure in terms of the resources and area used. With the addition of Verilog capability and power based design exploration a new version of the DG2VHDL tool suite, called now DG2HDL ver. 1.0, has been created.

Committee:
Prof. Leeser
Prof. Manolakos (advisor),
Dr. Stone (external member)