Ming Ming

An Architecture-Level Method for Predicting the Power Consumption of VLSI Processor Arrays for DSP Applications

DATE: March 30, 2004

ABSTRACT

Parallel processing VLSI array architectures have been used extensively to implement in hardware signal and image processing algorithms when high throughput is demanded. A CAD tool, DG2VHDL, was developed at Northeastern to automate the systematic algorithm-to-architecture mapping methodology and rapidly explore the available architectural solutions in terms of the latency and area. As power consumption is becoming an increasingly important quality metric in VLSI architectures design, power-aware design methodologies and tools are rapidly emerging. However, they are primarily targeting the circuit level due to the lack of architecture-level power modeling methods that would allow the systematic design space exploration for minimum power VLSI array architectures.

In his thesis we are attempting to close this gap. We have developed an architecture-level model that can be used to estimate accurately the power consumption of VLSI processor arrays with different structure but all for the same DSP problem instance. We have identified the critical architecture-level parameters that contribute to array power consumption and then constructed a linear model whose coefficients can be found using least squares fit. Using three different case studies (sorting, convolution, motion estimation), the proposed modeling method was used to explore the design space and identify minimum power processor array architectures. It is shown that in fact the proposed method can correctly rank the candidate array architectures for the same DSP problem in terms of power, before any hardware synthesis is attempted. Furthermore, for all the problem size instances of the three case studies, the average power estimation error remains less than 10%. We hav e also developed a methodology which, by using the coefficients of fitted models for small-size problem instances, can provide model coefficients for larger-size instances without severely compromising the power prediction accuracy. Power model coefficient libraries for the three case studies considered have been built using the proposed method. Finally, the method has been integrated into the DG2VHDL suite of CAD tools in order to add the important capability of automatic design exploration and synthesis for minimum power VLSI array architectures. To the best of our knowledge this is a unique feature that is offered only by DG2VHDL today.

Thesis Committee: Prof. Manolakos (advisor), Prof. Meleis, Dr. Andrew Stone (external member)