Biomedical Engineering Research

The Biomedical Signal Processing

The Biomedical Signal Processing works on the development of signal and image processing algorithms to extract useful information from biomedical and biological signals. Our overall goal is to modify and develop powerful advanced signal processing algorithms in order to apply them appropriately for the analysis of these signals. We seek to use the signal processing theory to advance significant biomedical and biological applications, and at the same time to use the requirements of the physical problems we are interested in to push the advancement of signal processing theory and practice.

The lab has an on-going collaborations with researchers at the CardioVascular Research and Training Institute (CVRTI) at the University of Utah and at MIT, at the Brigham and Women's Hospital of Harvard Medical School, and with Dr. Joseph Ayers of the Northeastern University Marine Science Center. Our work has been supported financially by the National Science Foundation, the Whitaker Foundation, Brigham and Women's Hospital, and the Northeastern University College of Engineering. NU Faculty: Professor Dana Brooks

Research Projects

Dynamo Systems with FPGAs in them are inherently hardware/software systems. The simplest of these systems have one host processor and one FPGA both of which are used for computation. We are developing tools to determine when to best make use of the FPGA hardware. Our tools are unique in that they take into account communication costs and overhead costs and not just the raw computational speedup from running an algorithm on FPGA hardware. Our tool focuses on image processing pipelines. It determines what to run in hardware and what in software, generates the pipeline implementation, and runs it. We will extend this work to other application domains as well as to more sophisticated systems with several FPGAs and several processors.

Embedded PowerPC
New FPGA devices have embedded processors on the chip with the reconfigurable logic. We are investigating how best to make use of these embedded processors and how best to interface them to the FPGA logic. In addition, we are investigating ways to quantify computation times for algorithms run on the different types of resources available, including the overhead costs incurred in the interfaces. The goal is to predict how best to partition an application between hardware and software. For this research, we are using software defined radio as a target application.

Variable Precision Arithmetic
Many of the applications used for FPGAs are scientific applications that require floating point representations of numbers. The goal of using FPGAs is to exploit low-level parallelism and to do as many computations in parallel as possible. In order to support both floating point representations and a high degree of parallelism, we have developed a library of FPGA components that implement basic floating point arithmetic functions including add, subtract, multiply, divide and square root. The hardware modules are fully parameterized. These components support the IEEE standard floating point formats, and also formats with reduced bit-widths to enable higher degrees of parallelism.

High Level Design Tool Evaluation

Applications In Reconfigurable Hardware:

Past Research Projects